Position includes test planning, test creation, characterization, data analysis, and silicon debug of high density embedded SRAM memories in leading edge process technologies. Applicant should be familiar with modern SRAM cell operation. Testing techniques, failure mechanisms, and debug processes are a plus.
Development and debug of test patterns and test flows
Ensuring device testability and manufacturability from development through production
Optimization of test flows for increased quality and cost improvement
Analysis of part failures leading to test flow improvement
Analysis of characterization data
Perform Test program integration, validation and release
Support HVM operation if needed
Possess Degree in Electrical or Electronics Engineering plus 4-5 years of applicable experience or Master Degree in Electrical or Electronics Engineering plus a minimum of 2 year of directly related experience.
Possess Java, Perl, C++ coding skills
Strong ATE test class/method development experience with Advantest 93k and/or T2K platform
Able to support System Level Testing activities if required